Cache Coherence in Intelligent Memory Systems

As microprocessor clock speeds continue to climb, it has become increasingly di cult to keep computations supplied with data from memory [P97] [GHI95] [MSM97]. One promising solution is to move some of the computation into memory. We focus upon Active Pages, a model of computation that can be implemented inexpensively in conventional DRAMs [OCS98] [OHK99]. Active Page memory systems are meant to accelerate computations on commodity workstations and PCs. An unanswered question with Active Pages, and intelligent memory proposals in general, is how to keep data coherent between cooperating processing elements. In the Active Pages programming model, this issue translates to coherence between the main processor caches and Active Page DRAM. Active Pages is a page-based model of computation which associates simple functions with each page of memory. For example, Java objects stored in memory may have functions bound to the Active Pages to perform pointer chasing for mark-and-sweep garbage collection. By partitioning computations between processor and Active Page memory, data intensive applications can execute up to 1000 times faster than on the same system using conventional memory. Previous implementations used software ushes to prevent cached data from becoming inconsistent with data modi ed by Active Pages in memory. The intelligent memory environment introduces several challenges in designing a coherent system. Because this technology is aimed at commodity desktop processors, even minor hardware changes become costly. The goal is to change as little as possible, incorporating the intelligent memory into existing processor coherence protocols. In addition, intelligent memory systems may have hundreds to thousands of computational units. This can become a burden to the communication network. The Active Pages system only allows sharing between computational units and the main processor, limiting the patterns of sharing in the system. This allows a basic communication network to sustain the coherence tra c from hundreds of processors. In this study, we analyze three methods of communication between the main processor and the Active Page memory system: explicit cache ushes, uncached variables, and hardware coherence mechanisms. We demonstrate that the limited sharing within the Active Page memory system makes hardware coherence mechanisms both e cient and easy to implement. For those who question even minimal modi cation to commodity memory systems, we also demonstrate that software cache management can perform comparably to hardware coherence. Ongoing work evaluates this tradeo between programmability and hardware modi cations.